There is a conventional output buffer circuit as shown in FIG. 2.
The configuration of the conventional output buffer circuit is now explained hereinafter with reference to FIG. 2.
The output buffer circuit comprises an output terminal OUT1 on which output data appears, a p-channel MOS transistor (hereinafter referred to as PMOS) 129 and an n-channel MOS transistor (hereinafter referred to as NMOS) 130.
An output transistor control circuit for controlling operations of these PMOS 129 and NMOS 130 is connected to gate electrodes of the PMOS 129 and NMOS 130. The output transistor control circuit comprises inverters (hereinafter referred to as INVs) 120, 122, 125, 133, negative-conjunction circuits (hereinafter referred to as NAND circuits) 123 and 127. The output transistor and the inverters and NAND circuits in the output transistor control circuit are connected to one another as follows.
A read instruction signal IN1 is supplied to an input terminal of the INV 120, and a node 121 is connected to an output terminal of the INV 120. The node 121 is connected to an input terminal of the INV 122, and a node 110 is connected to an output terminal of the INV 122. An output signal node 131, to which a signal corresponding to data to be outputted from the output terminal OUT1 is inputted, is connected to an input terminal of the INV 133 and a node 132 is connected to an output terminal of the INV 133. The node 110 and the node 132 are connected to an input terminal of the NAND circuit 123, and a node 124 is connected to an output terminal of the NAND circuit 123, respectively. The node 110 and the output signal node 131 are connected to an input terminal of the NAND circuit 127, and a node 128 is connected to an output terminal of the NAND circuit 127, respectively. The node 124 is connected to an input terminal of the INV 125 and a node 126 is connected to an output terminal of the INV 125.
A source of the PMOS 129 is connected to a power supply VCC (a high voltage power supply is generally referred to as VCC) having a potential level of e.g. 3.3 V through a parasitic reactance L2 of a power supply wire (a parasitic reactance generated along a path extending from a package terminal to an inside wiring chip). A gate of the PMOS 129 is connected to the node 128 and a drain thereof is connected to the output terminal OUT1. A source of the NMOS 130 is connected to a ground GND (a low voltage power supply is generally referred to as VSS or GND) having a potential level of e.g. 0 V through a parasitic reactance L1 of a power supply (a parasitic reactance generated along a path ending from a package terminal to an inside wiring chip). A gate of the NMOS 130 is connected to the node 126 and a drain thereof is connected to the output terminal OUT1.
Connected to the input terminal of the INV 120 is a control circuit CONT1 for outputting read instruction signal IN1 corresponding to states of /RAS (Row Address Strobe Signal), /CAS (Column Address Strobe Signal), /OE (Output Enable Strobe Signal) and /WE (Write Enable Signal) respectively serving as multiple external input signals.
The control circuit outputs the read instruction signal IN1 which changes from "L" level to "H" level in the states where the /WE (Write Enable Signal) is "H" level and the /RAS (Row Address Strobe Signal), /CAS (Column Address Strobe Signal) and /OE (Output Enable Strobe Signal) respectively change from "H" level to "L" level. A capacitor C1 (normally 100 pF) is connected between the output terminal OUT1 and the ground GND. The capacitor C1 is provided outside the chip.
A resistor R1 is connected between the output terminal OUT1 and a reference voltage supply unit for supplying a reference voltage V2 (normally 1.4 V). The output terminal OUT1 and the reference voltage supply unit are also provided outside the chip.
The resistor R1, the capacitor C1 and the reference voltage supply unit respectively provided outside the chip are needed for operating the output buffer circuit.
The operation of the output buffer circuit shown in FIG. 2 will be now described with reference to FIG. 3.
i) In case that "H" level is outputted from the output terminal OUT1 (lower part in FIG. 3).
In a period for not reading data, since the states of /RAS, /CAS, /OE and /WE serving as the external input signals hold "H" level, the control circuit CONT1 outputs the read instruction signal IN1 of "L" level.
In case that the read instruction signal IN1 is "L" level, the node 128 goes to "H" level and the node 126 goes to "L" level so that both the PMOS 129 and NMOS 130 are turned off. Accordingly, the output terminal OUT1 outputs "Hi-Z" level. Whereupon, the output terminal OUT1 of the present circuit goes to "V2 level" by the resistor R1 and the reference voltage supply unit respectively provided outside the chip. Since this "V2 level" is an intermediate level between "H" level and "L" level, it is recognized that "V2 level" equals to "Hi-Z" level as viewed from an external device connected to the output terminal OUT1.
When the states of the /RAS, /CAS and /OE change from "H" level to "L" level while the /WE holds "H" level, the read instruction signal IN1 changes from "L" level to "H" level. At this time, when the output signal node 131 is "H" level, the node 128 goes to "L" level and the node 126 goes to "L" level so that the PMOS 129 is turned on and the NMOS 130 is turned off. When the PMOS 129 is turned on, a current i2 flows as shown in FIG. 2 so that the potential level of the output terminal OUT1 gradually increases. When the potential level of the output terminal OUT1 reaches a given value (VOH, e.g., 2.0 V) or more, it is decided that the potential level of the output terminal OUT1 is "H" level.
Thereafter, the read instruction signal IN1 changes from "H" level to "L" level. When the read instruction signal IN1 changes from "H" level to "L" level, the node 128 goes to "H" level so that the PMOS 129 is turned off. When the PMOS 129 is turned off, the potential level of the output terminal OUT1 gradually decreases and finally goes to "Hi-Z" level. (Since the potential level of the output terminal OUT1 returns to "Hi-Z" level, the operation thereof is hereinafter referred to as output reset).
ii) In case that "L" level is outputted from the output terminal OUT1 (upper part in FIG. 3).
On the other hand, since the node 128 goes to "H" level and the node 126 goes to "H" level when the output signal node 131 is "L" level in case that the read instruction signal IN1 changes from "L" level to "H" level, the PMOS 129 is turned off and the NMOS 130 is turned on. When the NMOS 130 is turned on, a current i1 flows as shown in FIG. 2 so that the potential level of the output terminal OUT1 gradually decreases. When the potential level of the output terminal OUT1 reaches a given value (VOL, i.e., 0.8 V) or less, it is decided that the potential level of the output terminal OUT1 is "L" level.
Thereafter, the read instruction signal IN1 changes from "H" level to "L" level. When the output terminal OUT1 changes from "H" level to "L" level, the node 126 goes to "L" level so that the NMOS 130 is turned off. When the NMOS 130 is turned off, the potential level of the output terminal OUT1 gradually increases, and finally goes to "Hi-Z" level. (Since the potential level of the output terminal OUT1 returns to "Hi-Z" level, the operation thereof is hereinafter referred to as output reset).
However, there was a case in the conventional output buffer circuit that the potential applied to the power supply VCC wire and GND wire varies largely (noise is generated).
For example, suppose that "L" level is outputted from the output terminal OUT1 (upper part in FIG. 3).
When the read instruction signal IN1 changes from "H" level to "L" level, the NMOS 130 is turned off so that the current i1 is cut off. However, if the current i1 is cut off before the potential level of the output terminal OUT1 fully decreases to the GND level, a reaction is enforced by a parasitic reactance L1 along with the power supply wire to preserve the existing current flow, then the potential applied to the GND wire inside the chip instantaneously drops to a negative level. (potential drop V=(L component).times.(rate of change of current in terms of time).
Meanwhile, when "H" level is outputted from the output terminal OUT1 (lower part in FIG. 3), the potential which is applied to the power supply VCC wire inside the chip instantaneously drops to the potential level which is greater than VCC due to the effect of the parasitic reactance L2 on the power supply wire at the output reset time.
Further, there is a large capacitance between the power supply VCC and the ground GND, the potential applied to the power supply VCC wire inside the chip follows and varies.
When the potential applied to the power supply VCC wire the ground GND wire largely varies at the output reset time, there is a case that the control circuit CONT1 for outputting the read instruction signal IN1 erroneously recognizes the potential levels of multiple external input signals (/RAS, /CAS , /OE and /WE). As a result, there is a possibility that the read instruction signal IN1 of "H" level appears in a period other than a read period, and hence an improvement thereof is desired.